Infinite loop when simulating a Program Counter design with Icarus Verilog -

i implementing simple program counter adder following prototype:

module program_counter(input        enable_count,                        input        enable_overwrite,                        input[31:0]  overwrite_value,                        output[31:0] out); 

when simulating icarus verilog, infinite loop @ first tick on overwriting disabled , count enabled, internal register being therefore feeded output of pc adder (pc + 4).

i simplified issue basic piece of code d flip flop used 1-bit register:

module register(input in, input set, output out);      wire not_in;     wire q0;     wire not_q0;     wire not_q;      nand (q0, in, set);      not  (not_in, in);     nand (not_q0, not_in, set);      nand (out, q0, not_q);     nand (not_q, not_q0, out);  endmodule  module test;      reg  clock;     reg  in;     wire out;     wire not_out;      xor (x_out, out, 1);                // add     or  (muxed_out, x_out, in);         // mux      register r(muxed_out, clock, out);      initial     begin         $dumpfile("test.vcd");         $dumpvars(0, test);          $display("\tclock,\tin,\tout");         $monitor("\t%b,\t%x,\t%b",                  clock, in, out);          #0 assign in = 1;               // erase register         #0 assign clock = 1;          #1 assign in = 0;         #1 assign clock = 0;          #2 assign clock = 1;         #3 assign clock = 0;         #4 assign clock = 1;     end  endmodule 

the vcd output not show state change after simulation gets stuck.

my guess that, @ particular tick, adder feeding different value (continuously adding), not stable, simulator waiting value fixed , gets stuck.

is design correct (i.e. can synthesized , supposed work) ?

there's combinational loop: output of 'register' feeds input through xor/or gates in test. you've created ring oscillator.

if add following code inside register, can see happening:

  @(in) $display("@%d: in = %d", $time, in); 

you'll see bunch of these when run interpreter:

@                   1: in = 1 @                   1: in = 0 @                   1: in = 1 @                   1: in = 0 

it looks you're trying make enabled latch in 'register'. intended? edge triggered flip flop normal practice in synchronous design. you'd need 2 latches back-to-back that, standard (and easier) way in verilog this:

reg my_flop;  @(posedge clk)    my_flop <= input; 

if want latch, can inferred (but these tend error prone , discouraged):

always @(clk, input) begin     if (clk)         my_flop = input; end 

is there reason you're trying create these manually gates?