memory - please help me, don't read the file "mem.dat" -

description memory . vhdl

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity memory      generic(file_name: string:= "mem.dat"); port (addr: in std_logic_vector(7 downto 0);         data: out std_logic_vector(7 downto 0);         rd: in std_logic;         ld: in std_logic); end memory;  architecture memory of memory type t_rom_data array (15 downto 0) of std_logic_vector(7 downto 0); type rom_file_type file of character; file rom_file: rom_file_type; signal rom_data: t_rom_data; begin        process(addr,rd)     variable i: natural;     begin         if rd = '1'             := conv_integer(addr);             data <= rom_data(i) after 5ns;         else              data <= (others => 'z');         end if;     end process;      process(ld)     variable c: character;     begin         if ld='1'  file_open(rom_file,file_name,read_mode);             in 0 15 loop                 b in 7 downto 0 loop                     c:='u';                     if not(endfile(rom_file))  read(rom_file,c);                         while not(endfile(rom_file)) , c/='0' , c/='1' , c/='z' , c/='w'                         , c/='l' , c/='h' , c/='-' , c/='x' , c/='u' loop                             read(rom_file,c);                         end loop;                                        end if;                       if c='0' rom_data(i)(b) <= '0';                     elsif c='1' rom_data(i)(b) <='1';                     elsif c='z' rom_data(i)(b) <='z';                     elsif c='w' rom_data(i)(b) <='w';                     elsif c='l' rom_data(i)(b) <='l';                     elsif c='h' rom_data(i)(b) <='h';                     elsif c='-' rom_data(i)(b) <='-';                     elsif c='x' rom_data(i)(b) <='x';                     else rom_data(i)(b) <='u';                     end if;                  end loop;             end loop;             file_close(rom_file);          end if;`enter code here`     end process; end memory; 

error is: warning (10873): using initial value x (don't care) net "rom_data[15][7]" @ memory.vhd(17) warning (10873): using initial value x (don't care) net "rom_data[15][6]" @ memory.vhd(17) warning (10873): using initial value x (don't care) net "rom_data[15][5]" @ memory.vhd(17) warning (10873): using initial value x (don't care) net "rom_data[15][4]" @ memory.vhd(17) warning (10873): using initial value x (don't care) net "rom_data[15][3]" @ memory.vhd(17) warning (10873): using initial value x (don't care) net "rom_data[15][2]" @ memory.vhd(17) warning (10873): using initial value x (don't care) net "rom_data[15][1]" @ memory.vhd(17) warning (10873): using initial value x (don't care) net "rom_data[15][0]" @ memory.vhd(17) warning (10873): using initial value x (don't care) net "rom_data[14][7]" @ memory.vhd(17) warning (10873): using initial value x (don't care) net "rom_data[14][6]" @ memory.vhd(17) warning (10873): using initial value x (don't care) net "rom_data[14][5]" @ memory.vhd(17)

file "mem.dat" in same directory project. work in quartus

this question appears how initialise rom data file, synthesis. if case, running process load data memory (which requires file readable @ run time) not going work.

what can do, however, declare memory - not signal constant , declaration must have initialiser clause; allowed call function. , because initialiser evaluated during synthesis, can open, read , close files.

an example might like

type t_rom_data array (15 downto 0) of std_logic_vector(7 downto 0);  function init_rom return t_rom_data    type rom_file_type file of character;    file rom_file: rom_file_type;    variable temp : t_rom_data; begin    file_open(rom_file,file_name,read_mode);    in 0 15 loop       ...       temp(i) := ...    end loop;    file_close(rom_file);     return temp; end init_rom;  constant rom_data: t_rom_data := init_rom; 

with rom read process have written it.