VHDL: Is there a convenient way to assign ascii values to std_logic_vector? -

• in verilog, can assign string vector like:

  wire [39:0] hello; assign hello = "hello";  

• in vhdl, i'm having difficulty finding method this:

  signal hello : out std_logic_vector (39 downto 0); ... hello <= "hello"; 

i've been using:

hello <= x"65_68_6c_6c_6f"; 

which unclear , time consuming large strings.

i've looked @ textio package , thetxt_util package, neither seem clear on how interpret string , convert std_logic.

is there simple method of assigning ascii codes std_logic in vhdl?

here's minimal example:

library ieee; use ieee.std_logic_1164.all;  entity test port(    ctrl : in std_logic;    stdout : out std_logic_vector (39 downto 0) ); end entity;  architecture rtl of test    signal temp : std_logic_vector (39 downto 0); begin    stdout <= temp;    process(ctrl)    begin       if (ctrl = '0')          temp <= "hello"; -- x"68_65_6c_6c_6f";       else          temp <= "world";       end if;    end process;  end rtl; 

this 1 varies little morten's answer - uses 1 multiply, copies string instead of creating alias, uses additional variable , returns standard logic vector ascending index range.

from package called string_utils:

library ieee;  use ieee.numeric_std.all; -- ...     function to_slv(s: string) return std_logic_vector          constant ss: string(1 s'length) := s;          variable answer: std_logic_vector(1 8 * s'length);          variable p: integer;          variable c: integer;      begin          in ss'range loop             p := 8 * i;             c := character'pos(ss(i));             answer(p - 7 p) := std_logic_vector(to_unsigned(c,8));          end loop;          return answer;      end function;  

you add argument default specifying ascending/descending index range return value. you'd need provided argument non default.